For functional testing of RTL (Register Transfer Level) hardware models written in a Hardware Description Language (HDL) there is often a need to force values of some signals and then restore the normal operation of the design. This enables verification of smaller models, use of simpler testbenches, and performance of what-if analyses. Modern HDLs such as SystemVerilog and VHDL provide language constructs for forcing and releasing signal values.
Forcing and releasing of signal values is supported in simulation. To run the same tests in emulation, force/release constructs should also be supported in emulation. To make the same test produce the same results in simulation and in emulation (congruency mode), the full simulation semantics of force/release constructs should be supported in emulation for both simple and complex cases.
Usually formal verification tools ignore force/release constructs, thus creating a serious verification gap. A need continues to exist for the use of the same models in simulation/emulation and in formal verification to ensure that the verification results are consistent and reliable.